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Custom And Analog Layout Training

Custom and analog layout 6 months course focused on all the aspects starting from Digital design, basics of semiconductors, fabrication, Linux, TCL scripting, Layout fundamentals, and detailed understanding of Analog, standard cell, memory and IO layout including physical verification.

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Course Overview

Custom layout training is a 6 months course focused on all the aspects of layout including Analog layout, Memory layout, Standard cell layout and IO layout. Custom layout design course ensures that the student is prepared on all the essential aspects of Custom layout including VLSI Design flow, advanced digital design, CMOS, FinFET, various memory architectures, Standard cell, IO’s and detailed analog layout techniques. Course also includes training on Linux commands, version control, scripting and soft skill for effective interview performance.

Course also includes detailed sessions on semiconductors, Ohms law, Kirchoff law’s, Diode-operation, MOSFET’s, MOSEFT operations, second order effects, FinFET’s, and detailed fabrication process, which is followed by assignments and hands on projects.

Course also covers layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD. Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.

Analog layout techniques involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL’s, ADC’s, DAC’s, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.

  • VLSI Design Flow (Introduction)
  • Basic Electronics (Resistor, Capacitor, Current & Voltage)
  • Material Physics
  • Mosfet Physics
  • Digital Circuits & Stick Diagrams
  • Linux Comands
  • Small Circuits Simulator using Cadence Tool

  • How to do Layouts
  • Digital Layout Constructions & Verification
  • Analog Layout Construction
  • Matching
  • Shielding
  • EMIR
  • Antenna
  • Latchup
  • Short Channel Effects
  • IC Fabrication
  • Candidates Gets Placement support from this stage

  • Project Execution
  • PLL (Face lock Loop)
  • LDO
  • ADC
  • DAC (Digital to Analog Controls)
  • BGR ( Band Gap Reference)
  • Standard Cell Library Construction

  • Requirements
  • Design specification & architecture
  • RTL Coding
  • RTL integration
  • Functional verification
  • Synthesis
  • DFT
  • Physical Design
  • STA
  • Custom Layout
  • Physical Verification
  • Post Silicon Validation

  • Combinational logic
    • Number systems
    • Radix conversions
    • K-maps, min-terms, max terms
    • Logic gates
    • Realization of logic gates using mux’s and universal gates
    • Compliments (1/2/9/10’s complement)
    • Arithmetic operations using compliments
    • Boolean expression minimization, Dmorgan theorems
    • POS and SOP
    • Conversion and realization
    • Adders
      • Half adder
      • Full adder
    • Subtractor
      • Half subtractor
      • Full subtractor
    • Multiplexers
    • Realizing bigger Mux’s using smaller Mux’s
    • Implementing Adders and subtractors using Multiplexers
    • Decoders and Encoders
    • Implementing Decoders and Encoders using Mux and Demux
    • Bigger Decoder/Encoder using smaller Decoder/Encoder
    • Comparators
    • Implementing multi bit Comparators using 1-bit Comparator
  • Sequential logic
    • Latch, Flipflop
    • Latch, Flipflop using Gates or Mux’s
    • Different types of FFs
    • FF Truth table
    • Excitation tables
    • Realization of FF’s using other FF’s
    • Applications of FF’s, Latches
      • Counters
      • Shift registers
      • Synchronizers for clock domain crossing
      • FSM’s
      • Mealy, Moore FSM
      • Different encoding styles
      • Frequency dividers
      • Frequency multiplication
    • STA
      • Setup time, Hold time, timing closure
      • fixing setup time and hold time violations
      • Launch flop, capture flop

  • Linux/UNIX OS, Shell
  • Working with files, directories
  • Commonly used commands

  • Basic Passive and Active devices.
  • Ohms law, Kirchoff laws
  • Basic of circuit understanding

  • Transistors in hardware design
    • Significance of transistors in hardware design
    • Logic gate implementation using BJT, CMOS
    • MOSFET functionality
  • Semiconductors
    • What makes Semiconductor special element?
    • Classification of solids into three types
    • Conductor, Insulator, Semiconductor
    • Energy bands in Solids
    • Types of Semiconductors
    • Intrinsic Semiconductors
    • Extrinsic Semiconductors
    • Types of Extrinsic Semiconductors
    • N-type Extrinsic Semiconductor
    • P-type Extrinsic Semiconductor
    • Si, Ge – comparison
    • Types of current in Semiconductors – Drift, Diffusion
    • ion
  • PN Junction dioda
    • PN Junction – forward, reverse bias
    • V-I Characteristics of PN Junction Diode
    • Different types of Diode
    • Applications of Diode
  • BJT
    • BJT
    • BJT working principle?
    • How BJT can be used for large scale manufacturing
    • BJT fabrication steps
    • Types of BJT?
    • Why BJT is not used in for lower technology nodes?
    • Issues with BJT?
    • Advantages of BJT?
    • NAND gate using BJT?
  • Field Effect Transistor : FET
    • What is Field Effect Transistor?
    • Types of FET
    • NMOS
    • PMOS
    • CMOS
    • Fin
  • NMOS
    • NMOS
    • What is NMOS?
    • NMOS working principle?
    • Different voltages, currents, their equations
    • NMOS circuit representation
    • How NMOS works like a switch
    • How NMOS can be used for large scale manufacturing
    • NMOS fabrication steps
    • Types of NMOS?
    • Why CMOS is used instead of NMOS?
    • Issues with NMOS?
    • Advantages of NMOS?
    • NAND gate using NMOS?
  • CMOS
    • CMOS
    • What is CMOS?
    • CMOS working principle?
    • Different voltages, currents, their equations
    • CMOS circuit representation
    • How CMOS works like a switch
    • How CMOS can be used for large scale manufacturing
    • CMOS fabrication steps
    • Types of CMOS?
    • Issues with CMOS?
    • Advantages of CMOS?
    • NAND gate using CMOS?
    • CMOS second order effects?
  • FinFET
    • FinFET
    • What is FinFET?
    • FinFET working principle?
    • Different voltages, currents, their equations
    • CMOS circuit representation
    • How CMOS works like a switch
    • How FinFET can be used for large scale manufacturing
    • FinFET fabrication steps
    • Types of FinFET?
    • Issues with FinFET?
    • Advantages of FinFET?
    • NAND gate using FinFET?

  • Layers of CMOS
  • Depositing oxide layer
  • Photholithography
  • Masking
  • Ethching Layers
  • Formation of nwell
  • Self aligned gate fabrication process
  • Diffusion to create n+ and P+ regions
  • Metallization

  • Mismatches & matching
  • Failure mechanisms: Electromigration, IR drop, lod & stress effects, WPE, antenna effects, latch- up, ESD (with high voltage rules, EOS effects)
  • Noises & coupling
  • Different types of processes – advantages & disadvantages:
    • 1. Planar CMOS
    2. FDSOI
    3. SOI
    4. BI-CMOS
    5. Gallium arsenide
    6. Silicon-germanium
    7. Finfet
  • Full chip construction, scribe seal, pad frame, integration, and guidelines
  • Packaging

  • Design rule checks (DRC)
  • Layout versus schematic (LVS)
  • Electrical rule checks (ERC)
  • Antenna checks
  • Latch-up
  • Reliability checks like EM and IR analysis
  • Design for manufacturability (DFM) checks

  • High-speed analog layout
  • Handling clocks
  • Analog circuits & layout guidelines
  • Single & multi-stage differential OP-AMP layout
  • Current mirror layout
  • PLL, DLL, and oscillators
  • Ldo and other regulators
  • ADCS & DACS
  • Bandgap, temperature sensors & biases: Current & voltage bias lines
  • Large drivers
  • Input pair, differential routing, power routing, offset minimizing
  • Power/signal IR drop
  • Cross-talk and coupling
  • Electrostatic discharge (ESD)
  • Deep sub-micron layout issues
  • Shallow trench isolation (STI)
  • Well proximity effect (WPE)

  • Assignments and multiple hands-on projects
  • Best practices & interview questions

  • Floor
  • Planning
  • Schematic
  • Layout

    • AND ALSO

  • Standard cell layout of digital gates
  • Level shifter
  • Schmitt trigger
  • Single stage OP-AMP
  • 4-bit flash ADC
  • 4-bit DAC
  • Bandgap reference with start-up circuit
  • Low drop-out regulator circuit

  • Overview
  • Env Setup
  • Special Variables
  • Data Types
  • Variables
  • Operators
  • Decisions
  • Loops
  • Arrays, Strings, Lists, Dictionary
  • History and Redoing of commands
  • String Pattern Matching commands

  • Expertise on Digital & Analog design concepts
  • Exposure to basic layout concepts

  • Course presentations for all topics
  • Session notes
  • Lab documents with detailed steps
  • User guides
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Course Highlights
  • 1-1 Dedicated Mentor Support
  • 24/7 Tool Access
  • Multiple mock interviews
  • Industry Standard Projects
  • Support with resume update