• AHB Interconnect verification project used as reference design to learn UVM & OVM
• AHB Interconnect will be verified from scratch while teaching all aspects of UVM
• What is UVM? Need for a methodology?
• How UVM evolved?
  • OVM, AVM, RVM, NVM, eRM
• UVM class library
  • Classification of base classes in various categories
• OOP basics
  • Encapsulation
  • Inheritance
  • Polymorphism
  • Parameterized classes
  • Parameterized macros
  • Static properties and static methods
  • Abstract classes
    • Pure virtual methods
  • How above aspect correlates with UVM implementation.
• UVM Class Library, Macros, Utilities
  • Detailed overview of important UVM base classes, Macros and Utility classes.
• UVM TB Architecture
  • Setting up a UVM based testbench for APB protocol from scratch.
  • Significance of uvm_root in UVM based testbenches.
    • run_test, how it starts whole TB flow.
• Command line processor
• Reporting classes
  • Uvm_report_object
  • Uvm_report_handler
  • Uvm_report_server
  • Detailed examples on use of methods in these classes.
• Objections
• UVM Factory
• Configuration DB, Resource DB
  • Detailed usage of both data bases.
  • How config_db is related to resource_db?
  • Using config_db to change the testbench architecture.
• TLM1.0
  • Push
  • Pull
  • FIFO
  • Analysis
  • Complex example on AHB to AXI transaction conversion.
• Simulation Phases
  • UVM common phases
  • Scheduled phases
• Sequences, Sequencers
  • Default sequence
  • p_sequencer
  • m_sequencer
• Test case development
  • Different styles of mapping testcase to sequence
    • Using default sequence and scheduled phases
    • Using sequence start method
• Configuring TB Environment
  • Advanced aspects of developing a highly configurable test bench environment.
  • Concept of knobs of test case scenario generation
  • Using top level parameters to control the overall TB architecture
• AHB Protocol and AHB UVC development
  • Coding from scratch with detailed explanation of each aspect.
  • Setting up a highly configurable UVC to meet different TB requirements.
• Different testbench component coding
  • Monitor
  • Coverage
  • Scoreboard
  • Checkers
  • Assertions
• Different styles of sequence development
  • `uvm_do
  • Start_item and finish_item
  • Using existing sequences
• Sequence library
  • Creating complex test cases using sequence library
• Virtual Sequencer, Virtual sequences
• Different types of sequences used in test benches
  • Reset sequence
  • Power up sequence
  • interrupt handling sequence
  • DMA handling sequence
  • FSM verification sequence
• Layered sequence development
  • How to create multiple layers of sequences
  • Creating complex test cases using layered sequences
• Virtual sequence library
  • Creating test cases using virtual sequence library
• Synchronization classes
  • uvm_barrier
  • uvm_event
• Container classes
• Policy classes
  • uvm_printer
  • uvm_recorder
  • uvm_packer
  • uvm_comparer
• Comparators
  • In order comparator
  • Algorithmic comparator
• TLM2.0
  • Blocking transport
  • Non-blocking transport
• Register Layer development for USB2.0 core
  • Note: Doesn’t involve USB2.0 core verification
• Connecting multiple UVCs
  • How to setup a complex testbench environment with multiple UVC’s connected.
• uvm_heartbeat
  • How to check test bench status using heartbeat
• uvm_report_catcher
  • How to handle error testcases using report catcher
• Phase jumping
  • uvm_domain

• Protocol basics
  • Protocol overview
  • Protocol features
  • AMBA protocol overview
  • AXI Protocol basics
• SOC Architecture – Significance of AXI protocol
• AXI based system architecture
• Correlating AXI with APB protocol
  • Ports(signals) required for AXI protocol
• AXI Channels
  • Write & Read Channels
  • Handshaking using valid and ready
  • Write Channel Signals – Address, Data and Response
  • Read Channel Signals – Address and Data
• Timing diagrams
  • How to draw the timing diagrams?
  • Write Transaction Timing Diagram
  • Read Transaction Timing Diagram
• AXI transaction analysis for big endian and little endian architecture
• Wrap transactions – write and read
• Narrow transfers
• Data bus and strobe relation
• Aligned and unaligned transfers
• AXI signal encoding
• Responses in AXI
• Locked and exclusive transfers
• Overlapping, out of order, interleaved txs
• Interconnect role in out of order transaction
• Significance of ID in AXI protocol
• AXI Channel handshake dependency
• Cacheable and bufferable transactions
• Protected transactions
• AXI VIP and UVC development
  • Need for UVC?
  • Different types of UVC’s
  • UVC usage in module and SOC verification
  • Where Passive UVC are used?
  • UVC integration in to TB
  • AXI UVC architecture
  • AXI Transaction Definition
  • AXI UVC coding
  • AXI TB simulation and wave form analysis
  • AXI UVC integration
  • AXI scoreboard coding – Out of order tx handling

• Reading Specification
• Feature listing down
• Scenario Listing down
• Functional coverage listing down
• Coverage Implementation
• Testplan creation
• Testbench architecture development
• Testbench component coding
• Testcase coding and debug
• Assertions coding
• Regression setup
• Regression debug
• Verification closure
  • Regression closure
  • Functional & Code coverage closure

• Reading design specification
• How to read specification – understanding architecture, sub blocks, interfaces, registers
• Listing down features, scenarios
• Develop testplan
• Functional coverage point list down
• Develop Testbench architecture
• Testbench component coding and integration
• Develop sanity testcases(smoke tests)
• Bring up test bench environment using sanity testcases
• Develop rest of test bench components including monitor, coverage and scoreboard
• Register model(RAL) development and integration
• Register write-read, reset tests using front door and back door access
• Functional testcase coding using Register model
• Functional testcase debug using RTL, data flow and schematic tracing
• Setup regression using Python
• Debug regression failures
• Functional, Code and assertion coverage analysis
• Develop more functional tests for coverage improvement

• Introduction to Python
• What is Python?
• Python Scripts
• Print Functions
• Literals
• Quoting Rules
• Fundamentals of Python
• Numbers and Strings
• Lists and Tuples
• Dictionary
• Standard Input and Output
• Predefined file Handles
• Operators and Conditions
• String, Assignment, Arithmetic Operators
• Relational and Equality Operators
• Logical operators
• Regular Expressions
• Simple Statements and Modifies
• Pattern Matching
• The tr function
• Pattern Matching
• Loops
• Labels and Blocks
• While, Until, For
• Labels, Loops and loop control
• Foreach
• Working with Files
• User Defined file handles
• Open file for Writing, Reading, Appending
• Open for pipes
• Close, eof functions
• Arguments
• @ARGV array command line arguments
• ARGV and the Shift functions
• Array Built-in Functions
• Functions: grep, split, join, slice, pop, push
• Functions: shift, unshift, reverse, sort, chop, chomp
• Associative Array Functions
• Python Modules
• Subroutines
• Passing by reference, value
• Return statement
• Standard Perl Library
• @INC Array
• Packages and .pl files
• Require function
• Modules and .pm Files
• Objects and Object Oriented Python
• Object oriented Python
• Classes
• my function
• objects, methods
• destructors
• Inheritance
• Derives classes
• Python for VLSI flow automation
• Setting up complete regression flow till report generation
• Creating complete SOC Test bench Environment Structure
• Developing test cases using parameter input text file
• CSV file handling
  • Generating testbench using CSV file and user provided input
• Handling regression logs
• Parsing spreadsheet and writing spreadsheet.
• UVM Register Model Creation using spreadsheet
• Regression result speadsheet creation
• Regression result HTML creation
• Recursive directory manipulation

40+ detailed assignments covering all aspects of SV & UVM