• Follow Us On :
img img img img img
img

Advanced Custom and Analog Layout Training

Advanced Custom and analog layout training is a 4 months course targeted for working professional planning to pursue career as a layout design engineer or wants to learn advanced aspects of Custom and analog layout.

Best Seller   img

Advanced Custom and Analog Layout

Course Overview

Advanced Custom and analog layout training is a 4 months course targeted for working professional planning to pursue career as a layout design engineer or wants to learn advanced aspects of Custom and analog layout. Training focused on all the aspects of layout including Analog layout, Memory layout, Standard cell layout and IO layout.

Course also includes detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD. Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.

Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL’s, ADC’s, DAC’s, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.

  • Layout Editor Tool
  • Understanding the schematic symbols and parameters
  • Creating and managing libraries and cell
  • Commands for Layout editing.
  • Commands for schematic editing.
  • Verification : DRC and LVS
  • Antenna effect, latchup, Electromigration, IR Drop
  • Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
  • Resistor, Capacitor layout techniques
  • CMOS and BiCMOS layout techniques
  • Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop

  • Mismatches & Matching.
  • Failure Mechanism : Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD (with High voltage rules, EOS effects).
  • Noises & Coupling.
  • Different Types of process – Advantages & Disadvantages – Planar CMOS, FD-SOI, SOI, Bi-CMOS, Gallium Arsenide, Silicon-Germanium, Finfet.
  • Full Chip Construction, Scribe Seal, Pad Frame, Integration and guidelines.
  • Packaging.

  • Std Cell & Memories.
  • IO Layout Guidelines : High speed IOs and High Speed Interfaces.
  • Sense amplifier & Bit cell development
  • Why memory layout different than analog layout
  • Memory layout flow
  • Types of memory layout (SRAM/DRAM/ROM)
  • Introduction to SRAM memory layout
  • Fixing few manually created leaf-cell errors which impact
  • Abutment issues
  • Impact of IR, EM and DFM .
  • SRAM memory design architecture
  • Words line and address line
  • SRAM rows and column design
  • Building blocks of SRAM
  • Memory Bit cell
  • Row decoder
  • Word line driver
  • Sense amplifier
  • Control block
  • Misc digital logic.
  • Pitch Calculation for blocks.
  • Power Planning

  • High speed Analog Layout
  • RF Layout guidelines with Transmission lines and inductor concepts
  • Handling clocks
  • Analog Circuits & Layout guidelines
  • Single & Multi stage differential opamp layout
  • current mirror layout
  • PLL, DLL and Oscillators
  • LDO and other regulators
  • ADCs & DACs
  • Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines
  • Large drivers
  • input pair, differential routing, Power routing, offset minimising
  • Power/Signal IR Drop
  • cross-talk and coupling
  • Electrostatic Discharge
  • Deep Sub-micron Layout Issues
  • Shallow Trench Isolation (LOD)
  • Well Proximity Effect

  • Design Rule Checks
  • Layout Versus Schematic (LVS)
  • Electrical Rule Checks (ERC)
  • Antenna Checks
  • Latch-up
  • Reliability checks like EM and IR analysis
  • Design for manufacturability (DFM)checks
  • Electrostatic discharge (ESD) path checks

  • Assignments and multiple hands on projects
  • Best Practices & Interview Questions.

  • Course presentations for all topics
  • Session notes
  • Lab documents with detailed steps
  • User guides

  • Expertise on Digital & Analog design concepts
  • Exposure to basic layout concepts
img
Course Highlights
  • 1-1 Dedicated Mentor Support
  • 24/7 Tool Access
  • Multiple mock interviews
  • Industry Standard Projects
  • Support with resume update