Physical Verification Training
Physical Verification training is a four months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a Physical verification engineer
Course Overview
Physical Verification training is a four months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a Physical verification engineer. Physical Verification course ensures that a fresher/experienced engineer is prepared on all the aspects of Physical Verification including DRCs, LVS, ERC, Antenna Checks, Latchup, Exposure to the Importance of reliability checks like EM and IR analysis Design for manufacturability (DFM)checks, Electrostatic discharge (ESD) path checks.
Course will consist of 70% exposure to hands on projects and 30% theory sessions.
Course includes training on ASIC flow, Advanced Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO’s and Analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Course includes 20+ detailed labs & assignments covering all aspects of Physical Verification with multiple hands on projects.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchhoff law’s, Diode-operation, CMOS operations, second order effects, FinFET’s, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures with detailed physical verification checks for the same.
- Requirements
- Design specification & architecture
- RTL Coding
- RTL integration
- Functional verification
- Synthesis
- DFT
- Physical Design
- STA
- Custom Layout
- Physical Verification
- Post Silicon Validation
Digital Design syllabus
- Linux/UNIX OS, Shell
- Working with files, directories
- Commonly used commands
- Conductor, Semiconductor & Insulators -> Intrinsic & Extrinsic Semiconductor.
- Basic Passive and Active devices.
- Ohms law, Kirchoff laws
- Basic of circuit understanding
- MOSFET Basics, Operations, few simple circuits & second order effects.
- MOSFET Detailed fabrication process.
- FinFET working, Fabrication, advantages & disadvantages.
- Layout Editor Tool
- Understanding the schematic symbols and parameters
- Creating and managing libraries and cell
- Commands for Layout editing.
- Commands for schematic editing.
- Verification : DRC and LVS
- Antenna effect, latchup, Electromigration, IR Drop
- Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
- Resistor, Capacitor layout techniques
- CMOS and BiCMOS layout techniques
- Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop
- Design Rule Checks
- Layout Versus Schematic (LVS)
- Electrical Rule Checks (ERC)
- Antenna Checks
- Latch-up
- Reliability checks like EM and IR analysis
- Design for manufacturability (DFM)checks
- Electrostatic discharge (ESD) path checks
- Multiple projects with detailed Physical verification analysis
- Assignments and multiple hands on projects
- Best Practices & Interview Questions.
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Expertise on Digital & Analog design concepts
- Exposure to basic layout concepts
Course Highlights
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple mock interviews
- Industry Standard Projects
- Support with resume update